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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7862 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 simultaneous sampling dual 250 ksps 12-bit adc functional block diagram clock dgnd db0 busy rd cs convst AD7862 conversion control logic v a1 agnd v ref +2.5v reference 2k w agnd track/ hold v dd db11 output latch mux a0 12-bit adc 12-bit adc track/ hold mux signal scaling signal scaling signal scaling signal scaling v b1 v a2 v b2 features two fast 12-bit adcs four input channels simultaneous sampling & conversion 4 m s throughput time single supply operation selection of input ranges: 6 10 v for AD7862-10 6 2.5 v for AD7862-3 0 v to 2.5 v for AD7862-2 high speed parallel interface low power, 60 mw typ power saving mode, 50 m w typ overvoltage protection on analog inputs 14-bit pin compatible upgrade (ad7863) applications ac motor control uninterrupted power supplies data acquisition systems communications general description the AD7862 is a high speed, low power, dual 12-bit a/d converter that operates from a single +5 v supply. the part contains two 4 m s successive approximation adcs, two track/ hold amplifiers, an internal +2.5 v reference and a high speed parallel interface. there are four analog inputs that are grouped into two channels (a & b) selected by the a0 input. each channel has two inputs (v a1 & v a2 or v b1 & v b2 ) that can be sampled and converted simultaneously thus preserving the relative phase information of the signals on both analog inputs. the part accepts an analog input range of 10 v (AD7862-10), 2.5 v (AD7862-3) and 0C2.5 v (AD7862-2). overvoltage protection on the analog inputs for the part allows the input voltage to go to 17 v, 7 v or +7 v, respectively, without causing damage. a single conversion start signal ( convst ) places both track/ holds into hold simultaneously and initiates conversion on both inputs. the busy signal indicates the end of conversion, and at this time the conversion results for both channels are avail- able to be read. the first read after a conversion accesses the result from v a1 or v b1 , while the second read accesses the result from v a2 or v b2 , depending on whether the multiplexer select a0 is low or high, respectively. data is read from the part via a 12-bit parallel data bus with standard cs and rd signals. in addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the part is also specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio. the AD7862 is fabricated in analog devices linear compat- ible cmos (lc 2 mos) process, a mixed technology process that combines precision bipolar circuits with low power cmos logic. it is available in 28-lead ssop, soic and dip. product highlights 1. the AD7862 features two complete adc functions allowing simultaneous sampling and conversion of two channels. each adc has a 2-channel input mux. the conversion result for both channels is available 3.6 m s after initiating conversion. 2. the AD7862 operates from a single +5 v supply and consumes 60 mw typ. the automatic power-down mode, where the part goes into power down once conversion is complete and wakes up before the next conversion cycle, makes the AD7862 ideal for battery-powered or portable applications. 3. the part offers a high speed parallel interface for easy con- nection to microprocessors, microcontrollers and digital signal processors. 4. the part is offered in three versions with different analog input ranges. the AD7862-10 offers the standard industrial input range of 10 v; the AD7862-3 offers the common signal processing input range of 2.5 v; while the AD7862-2 can be used in unipolar 0 v C +2.5 v applications. 5. the part features very tight aperture delay matching between the two input sample-and-hold amplifiers.
C2C rev. 0 AD7862Cspecifications ab s parameter version 1 version version units test conditions/comments sample and hold C3 db small signal bandwidth 3 3 3 mhz typ aperture delay 20 20 20 ns typ aperture jitter 100 100 100 ps typ aperture delay matching 200 200 200 ps typ dynamic performance 2 f in = 100.0 khz, f s = 250 ksps signal to (noise+distortion) ratio 3 @ +25 c 70 71 70 db min t min to t max 70 70 70 db min total harmonic distortion 3 C78 C78 C78 db max peak harmonic or spurious noise 3 C85 C85 C85 db typ intermodulation distortion 3 fa = 49 khz, fb = 50 khz 2nd order terms C85 C85 C85 db typ 3rd order terms C85 C85 C85 db typ channel to channel isolation 3 C80 C80 C80 db max f in = 100 khz sine wave dc accuracy any channel resolution 12 12 12 bits minimum resolution for which no missing codes are guaranteed 12 12 12 bits relative accuracy 3 1 1 1 lsb max typically 0.4 lsb differential nonlinearity 3 1 1 1 lsb max positive gain error 3 4 3 4 lsb max positive gain error match 3 4 3 4 lsb max AD7862-10 negative gain error 3 4 3 4 lsb max bipolar zero error 4 3 4 lsb max bipolar zero error match 4 3 4 lsb max AD7862-3 negative gain error 3 4 3 4 lsb max bipolar zero error 4 3 4 lsb max bipolar zero error match 4 3 4 lsb max AD7862-2 unipolar offset error +4 +3 +4 lsb max unipolar offset error match 4 3.5 4 lsb max analog inputs AD7862-10 input voltage range 10 10 10 volts input input resistance 24 24 24 k w min AD7862-3 input voltage range 2.5 2.5 2.5 volts input input resistance 6 6 6 k w min AD7862-2 input voltage range +2.5 +2.5 +2.5 volts input input current 500 500 500 na max reference input/output ref in input voltage range 2.375/2.625 2.375/2.625 2.375/2.625 v min/v max 2.5 v 5% ref in input capacitance 4 10 10 10 pf max ref out output voltage 2.5 2.5 2.5 v nom ref out error @ +25 c 10 10 10 mv max ref out error t min to t max 25 25 25 mv max ref out temperature coefficient 25 25 25 ppm/ c typ ref out output impedance 2 2 2 k w nom logic inputs input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 m a max input capacitance, c in 4 10 10 10 pf max (v dd = +5 v 6 5%, agnd = dgnd = 0 v, ref = internal. all specifications t min to t max unless otherwise noted.)
C3C rev. 0 AD7862 ab s parameter version 1 version version units test conditions/comments logic outputs output high voltage, v oh 4.0 4.0 4.0 v min i source = 200 m a output low voltage, v ol 0.4 0.4 0.4 v max i sink = 1.6 ma db11Cdb0 floating-state leakage current 10 10 10 m a max floating-state capacitance 4 10 10 10 pf max output coding AD7862-10, AD7862-3 twos complement ad7863-2 straight (natural) binary conversion rate conversion time 3.6 3.6 3.6 m s max for both channels track/hold acquisition time 2, 3 0.3 0.3 0.3 m s max power requirements v dd +5 +5 +5 v nom 5% for specified performance i dd normal mode 15 15 15 ma max standby mode 25 25 25 m a max logic inputs = 0 v or v dd power dissipation normal mode 75 75 75 mw max typically 60 mw standby mode 125 125 125 m w max typically 75 m w notes 1 temperature ranges are as follows: a, b versions: C40 c to +85 c; s version: C55 c to +125 c. 2 performance measured through full channel (multiplexer, sha and adc). 3 see terminology. absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v analog input voltage to agnd AD7862-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 v AD7862-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v AD7862-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v reference input voltage to agnd . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . C0.3 v to v dd + 0.3 v digital output voltage to dgnd . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial (a, b version) . . . . . . . . . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic dip package, power dissipation . . . . . . . . . . 670 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 116 c/w lead temperature, (soldering 10 sec) . . . . . . . . . . +260 c ceramic dip package, power dissipation . . . . . . . . . 670 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 116 c/w lead temperature, (soldering 10 sec) . . . . . . . . . . +260 c soic package, power dissipation . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 110 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c ssop package, power dissipation . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 110 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide input relative temperature package package model input accuracy range description option AD7862ar-10 10 v 1 lsb C40 c to +85 c 28-bit small outline package r-28 AD7862br-10 10 v 1 lsb C40 c to +85 c 28-bit small outline package r-28 AD7862ars-10 10 v 1 lsb C40 c to +85 c 28-bit shrink small outline package rs-28 AD7862an-10 10 v 1 lsb C40 c to +85 c 28-bit plastic dip n-28 AD7862sq-10 10 v 1 lsb C55 c to +125 c 28-bit cerdip q-28 AD7862ar-3 2.5 v 1 lsb C40 c to +85 c 28-bit small outline package r-28 AD7862br-3 2.5 v 1 lsb C40 c to +85 c 28-bit small outline package r-28 AD7862ars-3 2.5 v 1 lsb C40 c to +85 c 28-bit shrink small outline package rs-28 AD7862an-3 2.5 v 1 lsb C40 c to +85 c 28-plastic dip n-28 AD7862ar-2 0 v to 2.5 v 1 lsb C40 c to +85 c 28-bit small outline package r-28 AD7862ars-2 0 v to 2.5 v 1 lsb C40 c to +85 c 28-bit shrink small outline package rs-28 4 sample tested @ +25 c to ensure compliance. specifications subject to change without notice.
AD7862 C4C rev. 0 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7862 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. timing characteristics 1, 2 a, b s parameter versions version units test conditions/comments t conv 3.6 3.6 m s max conversion time t acq 0.3 0.3 us max acquisition time parallel interface t 1 0 0 ns min cs to rd setup time t 2 0 0 ns min cs to rd hold time t 3 35 45 ns min convst pulse width t 4 35 45 ns min read pulse width t 5 3 12 12 ns min data access time after falling edge of rd 60 70 ns max t 6 4 5 5 ns min bus relinquish time after rising edge of rd 30 40 ns max t 7 40 40 ns min time between consecutive reads notes 1 sample tested at +25 c to ensure compliance. all input signals are measured with tr = tf = 1 ns (10% to 90% of +5 v) and timed from a voltage level of +1.6 v. 2 see figure 1. 3 measured with the load circuit of figure 2 and defined as the time required for an output to cross 0.8 v or 2.0 v. 4 these times are derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. specifications subject to change without notice. (v dd = +5 v 6 5%, agnd = dgnd = 0 v, ref = internal. all specifications t min to t max unless otherwise noted.) v a1 v a2 v b1 v b2 t 3 t 1 t 2 t 4 t 5 t 6 t conv t 7 convst busy a0 cs rd data ......... ......... figure 1. timing diagram +1.6v 1.6ma 200? 50pf to output pin figure 2. load circuit for access time and bus relinquish time
AD7862 C5C rev. 0 pin function description pin mnemonic description 1 nc no connect 2 db11 data bit 11 (msb). three-state ttl output. output coding is twos complement for the AD7862- 10 and AD7862-3. output coding is straight (natural) binary for the AD7862-2. 3C6 db10Cdb7 data bit 10 to data bit 7. three-state ttl outputs. 7 dgnd digital ground. ground reference for digital circuitry. 8 convst convert start input. logic input. a high to low transition on this input puts both track/holds into their hold mode and starts conversion on both channels. 9C15 db6Cdb0 data bit 6 to data bit 0. three-state ttl outputs. 16 agnd analog ground. ground reference for mux, track/hold, reference and dac circuitry. 17 v b2 input number 2 of channel b. analog input voltage ranges of 10 v (AD7862-10), 2.5 v (AD7862-3) and 0 vC2.5 v (AD7862-2). 18 v a2 input number 2 of channel a. analog input voltage ranges of 10 v (AD7862-10), 2.5 v (AD7862-3) and 0 vC2.5 v (AD7862-2). 19 vref reference input/output. this pin is connected to the internal reference through a series resistor and is the output reference source for the analog-to-digital converter. the nominal reference voltage is 2.5 v, and this appears at the pin. 20 a0 multiplexer select. this input is used in conjunction with rd and cs low to enable the data outputs. with a0 logic low, one read after a conversion will read the data from each of the adcs in the sequence, v a1 , v a2 , and a subsequent read, when a0 goes high, reads the data from v b1 , v b2 . 21 cs chip select input. active low logic input. the device is selected when this input is active. 22 rd read input. active low logic input. this input is used in conjunction with a0 and cs low to enable the data outputs. with a0 logic low, one read after a conversion will read the data from each of the adcs in the sequence, v a1 , v a2 , and a subsequent read, when a0 goes high, reads the data from v b1, v b2 . 23 busy busy output. the busy output is triggered high by the falling edge of convst and remains high until conversion is completed. 24 vdd analog and digital positive supply voltage, +5.0 v 5%. 25 v a1 input number 1 of channel a. analog input voltage ranges of 10 v (AD7862-10), 2.5 v (AD7862-3) and 0 vC2.5 v (AD7862-2). 26 v b1 input number 1 of channel b. analog input voltage ranges of 10 v (AD7862-10), 2.5 v (AD7862-3) and 0 vC2.5 v (AD7862-2). 27 agnd analog ground. ground reference for mux, track/hold, reference and dac circuitry. 28 nc no connect pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 AD7862 nc = no connect nc v a1 v b1 agnd nc db11 db10 db9 rd busy v dd db8 db7 dgnd convst db6 db5 v ref a0 cs db4 db3 db2 db1 v a2 db0 agnd v b2
AD7862 C6C rev. 0 terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7862 it is defined as: thd db () = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 and v 5 are the rms amplitudes of the second through the fifth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the l argest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2 fa + fb), (2 fa C fb), (fa + 2 fb) and (fa C 2 fb). the AD7862 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale 100 khz sine wave signal to each of the four inputs individually. these, in turn, are individually referenced to the other three channels whose inputs are grounded, and the adc output is measured to determine the level of crosstalk from the other channel. the figure given is the worst case across all four channels. relative accuracy relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. positive full-scale error this is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 vref C 3/2 lsb (AD7862-10 10 v range) or vref C 3/2 lsb (AD7862-3, 2.5 v range) after the bipolar offset error has been adjusted out. positive full-scale error (AD7862-2, 0 v to 2.5 v) this is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal vref C 3/2 lsb after the unipolar offset error has been adjusted out. bipolar zero error (AD7862-10, 6 10 v, AD7862-3, 6 2.5 v) this is the deviation of the midscale transition (all 1s to all 0s) from the ideal agnd C 1/2 lsb. unipolar offset error (AD7862-2, 0 v to 2.5 v) this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal agnd + 1/2 lsb. negative full-scale error (AD7862-1, 6 10 v; AD7862-3, 6 2.5 v) this is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal C4 vref + 1/2 lsb (AD7862-10 10 v range) or Cvref + 1/2 lsb (AD7862-3, 2.5 v range) after bipolar zero error has been adjusted out. track/hold acquisition time track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion (the point at which the track/hold returns to track mode). it also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected v ax/bx input of the AD7862. it means that the user must wait for the duration of the track/hold acquisition time, after the end of conversion or after a channel change/step input change to v ax/bx , before starting another conversion to ensure that the part operates to specification.
AD7862 C7C rev. 0 converter details the AD7862 is a high speed, low power, dual 12-bit a/d converter that operates from a single +5 v supply. the part contains two 4 m s successive approximation adcs, two track/ hold amplifiers, an internal +2.5 v reference and a high speed parallel interface. there are four analog inputs that are grouped into two channels (a & b) selected by the a0 input. each channel has two inputs (v a1 & v a2 or v b1 & v b2 ) that can be sampled and converted simultaneously thus preserving the relative phase information of the signals on both analog inputs. the part accepts an analog input range of 10 v (AD7862-10), 2.5 v (AD7862-3) and 0 vC2.5 v (AD7862-2). overvoltage protection on the analog inputs for the part allows the input voltage to go to 17 v, 7 v or +7 v, respectively, without causing damage. the AD7862 has two operating modes, the high sampling mode and the auto sleep mode where the part automatically goes into sleep after the end of conversion. these modes are discussed in more detail in the timing and control section. conversion is initiated on the AD7862 by pulsing the convst input. on the falling edge of convst , both on-chip track/ holds are placed into hold simultaneously, and the conversion sequence is started on both channels. the conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. the busy signal indicates the end of conversion, and at this time the conversion results for both channels are available to be read. the first read after a conver- sion accesses the result from v a1 or v b1 while the second read accesses the result from v a2 or v b2 , depending on whether the multiplexer select a0 is low or high, respectively. data is read from the part via a 12-bit parallel data bus with standard cs and rd signals. conversion time for the AD7862 is 3.6 m s in the high sampling mode (6 m s for the auto sleep mode), and the track/hold acquisition time is 0.3 m s. to obtain optimum performance from the part, the read operation should not occur during the conversion or during 300 ns prior to the next conversion. this allows the part to operate at throughput rates up to 250 khz and achieve data sheet specifications. track/hold section the track/hold amplifiers on the AD7862 allow the adcs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. the input bandwidth of the track/hold is greater than the nyquist rate of the adc even when the adc is operated at its maximum throughput rate of 250 khz (i.e., the track/hold can handle input frequencies in excess of 125 khz). the track/hold amplifiers acquire input signals to 12-bit accuracy in less than 400 ns. the operation of the track/holds is essentially transparent to the user. the two track/hold amplifi- ers sample their respective input channels simultaneously on the falling edge of convst . the aperture time for the track/holds (i.e., the delay time between the external convst signal and the track/hold actually going into hold) is typically 15 ns and, more importantly, is well matched across the two track/holds on one device and also well matched from device to device. this allows the relative phase information between different input channels to be accurately preserved. it also allows multiple AD7862s to sample more than two channels simultaneously. at the end of conversion, the part returns to its tracking mode. the acquisition time of the track/hold amplifiers begins at this point. reference section the AD7862 contains a single reference pin, labelled vref, which either provides access to the parts own +2.5 v reference or to which an external +2.5 v reference can be connected to provide the reference source for the part. the part is specified with a +2.5 v reference voltage. errors in the reference source will result in gain errors in the AD7862s transfer function and will add to the specified full-scale errors on the part. on the AD7862-10 and the AD7862-3, it will also result in an offset error injected in the attenuator stage. the AD7862 contains an on-chip +2.5 v reference. to use this reference as the reference source for the AD7862, simply connect a 0.1 m f disc ceramic capacitor from the vref pin to agnd. the voltage that appears at this pin is internally buffered before being applied to the adc. if this reference is required for use external to the AD7862, it should be buffered as the part has a fet switch in series with the reference output, resulting in a source impedance for this output of 3 k w nominal. the tolerance on the internal reference is 10 mv at 25 c with a typical temperature coefficient of 25 ppm/ c and a maximum error over temperature of 25 mv. if the application requires a reference with a tighter tolerance or the AD7862 needs to be used with a system reference, the user has the option of connecting an external reference to this vref pin. the external reference will effectively overdrive the internal reference and provide the reference source for the adc. the reference input is buffered before being applied to the adc with the maximum input current of 100 m a. suitable reference sources for the AD7862 include the ad680, ad780 and ref43 precision +2.5 v references. circuit description analog input section the AD7862 is offered as three part types; the AD7862-10, which handles a 10 v input voltage range; the AD7862-3, which handles input voltage range 2.5 v; and the AD7862-2, which handles a 0 v to +2.5 v input voltage range. agnd AD7862-10/AD7862-3 v ax v ref track/ hold to adc reference circuitry to internal comparator r3 r2 r1 mux 2k w +2.5v reference figure 3. AD7862-10/-3 analog input structure figure 3 shows the analog input section for the AD7862-10 and AD7862-3. the analog input range of the AD7862-10 is 10 v into an input resistance of typically 33 k w . the analog input range of the AD7862-3 is 2.5 v into an input resistance of typically 12 k w . this input is benign with no dynamic charging
AD7862 C8C rev. 0 currents, as the resistor stage is follo wed by a high input impedance stage of the track/hold amplifier. for the AD7862-10, r1 = 30 k w , r2 = 7.5 k w , and r3 = 10 k w . for the AD7862-3, r1 = r2 = 6.5 k w and r3 is open circuit. for the AD7862-10 and AD7862-3, the designed code transi- tions occur on successive integer lsb values (i.e., 1 lsb, 2 lsbs, 3 lsbs . . .). output coding is twos complement binary with 1 lsb = fs/4096. the ideal input/output transfer function for the AD7862-10 and AD7862-3 is shown in table i. table i. ideal input/output code table for the AD7862-10/-3 analog input l digital output code transition +fsr/2 C 1 lsb 2 011 . . . 110 to 011 . . . 111 +fsr/2 C 2 lsbs 011 . . . 101 to 011 . . . 110 +fsr/2 C 3 lsbs 011 . . . 100 to 011 . . . 101 gnd + 1 lsb 000 . . . 000 to 000 . . . 001 gnd 111 . . . 111 to 000 . . . 000 gnd C 1 lsb 111 . . . 110 to 111 . . . 111 Cfsr/2 + 3 lsbs 100 . . . 010 to 100 . . . 011 Cfsr/2 + 2 lsbs 100 . . . 001 to 100 . . . 010 Cfsr/2 + 1 lsb 100 . . . 000 to 100 . . . 001 notes 1 fsr is full-scale range = 20 v (AD7862-10) and = 5 v (AD7862-3) with ref in = +2.5 v. 2 1 lsb = fsr/4096 = 4.883 mv (AD7862-10) and 1.22 mv (AD7862-3) with ref in = +2.5 v. the analog input section for the AD7862-2 contains no biasing resistors, and the v ax/bx pin drives the input to the multiplexer and track/hold amplifier circuitry directly. the analog input range is 0 v to +2.5 v into a high impedance stage with an input current of less than 500 na. this input is benign with no dynamic charging currents. once again, the designed code transitions occur on successive integer lsb values. output coding is straight (natural) binary with 1 lsb = fs/4096 = 2.5 v/4096 = 0.61 mv. table ii shows the ideal input/output transfer function for the AD7862-2. table ii. ideal input/output code table for the AD7862-2 analog input 1 digital output code transition +fsr C 1 lsb 2 111 . . . 110 to 111 . . . 111 +fsr C 2 lsb 111 . . . 101 to 111 . . . 110 +fsr C 3 lsb 111 . . . 100 to 111 . . . 101 gnd + 3 lsb 000 . . . 010 to 000 . . . 011 gnd + 2 lsb 000 . . . 001 to 000 . . . 010 gnd + 1 lsb 000 . . . 000 to 000 . . . 001 notes 1 fsr is full-scale range and is 2.5 v for AD7862-2 with vref = +2.5 v. 2 1 lsb = fsr/4096 and is 0.61 mv for AD7862-2 with vref = +2.5 v. offset and full-scale adjustment in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the adc. invariably, some applications will require the input signal to span the full analog input dynamic range. in such applications, offset and full-scale error will have to be adjusted to zero. figure 4 shows a circuit that can be used to adjust the offset and full-scale errors on the AD7862 (v a1 on the AD7862-10 version is shown for example purposes only). where adjustment is required, offset error must be adjusted before full-scale error. this is achieved by trimming the offset of the op amp driving the analog input of the AD7862 while the input voltage is a 1/2 lsb below analog ground. the trim procedure is as follows: apply a voltage of C2.44 mv (C1/2 lsb) at v a1 (see figure 4) and adjust the op amp offset voltage until the adc output code flickers between 1111 1111 1111 and 0000 0000 0000. v 1 r1 10k w r2 500 w r3 10k w agnd AD7862* *additional pins omitted for clarity input range = 10v 10k w r5 10k w r4 v a1 figure 4. full-scale adjust circuit gain error can be adjusted at either the first code transition (adc negative full scale) or the last code transition (adc positive full scale). the trim procedures for both cases are as follows: positive full-scale adjust apply a voltage of +9.9927 v (fs/2 C 3/2 lsbs) at v a1 . adjust r2 until the adc output code flickers between 0111 1111 1110 and 0111 1111 1111. negative full-scale adjust apply a voltage of C9.9976 v (Cfs + 1/2 lsb) at v a1 and adjust r2 until the adc output code flickers between 1000 0000 0000 and 1000 0000 0001. an alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the vref pin until the full-scale error for any of the channels is adjusted out. the good full-scale matching of the channels will ensure small full-scale errors on the other channels. timing and control figure 5a shows the timing and control sequence required to obtain optimum performance (mode 1) from the AD7862. in the sequence shown, a conversion is initiated on the falling edge of convst . this places both track/holds into hold simulta- neously, and new data from this conversion is available in the output register of the AD7862 3.6 m s later. the busy signal indicates the end of conversion, and at this time the conversion results for both inputs are available to be read. a second conversion is then initiated. if the multiplexer select a0 is low, the first and second read pulses after the first c onversion accesses the result from channel a (v a1 and v a2 respectively). the third
AD7862 C9C rev. 0 and fourth read pulses, after the second conversion and a0 high, access the result from channel b (v b1 and v b2 respectively). a0s state can be changed any time after the convst goes high, i.e., track/holds into hold, and 400 ns prior to the next falling edge of convst . data is read from the part via a 12-bit parallel data bus with standard cs and rd signal, i.e., the read operation consists of a negative going pulse on the cs pin combined with two negative going pulses on the rd pin (while the cs is low), accessing the two 12-bit results. once the read operation has taken place, a further 300 ns should be allowed before the next falling edge of convst to optimize the settling of the track/hold amplifier before the next conversion is initiated. with the internal clock frequency at its maximum (3.7 mhznot accessible externally), the achievable throughput rate for the part is 3.6 m s (conversion time) plus 100 ns (read time) plus 0.3 m s (acquisition time). this results in a minimum throughput time of 4 m s (equivalent to a throughput rate of 250 khz). read options apart from the read operation described above and displayed in figure 5a, other cs and rd combinations can result in different channels/inputs being read in different combinations. suitable combinations are shown in figures 5b through 5d. v a1 v a2 cs rd data figure 5b. read option a v a1 v a2 cs rd data v a1 figure 5c. read option b v a1 v b1 a0 cs rd data figure 5d. read option c operating modes mode 1 operation (high sampling performance) the timing diagram in figure 5a is for optimum performance in operating mode 1 where the falling edge of convst starts conversion and puts the track/hold amplifiers into their hold mode. this falling edge of convst also causes the busy signal to go high to indicate that a conversion is taking place. the busy signal goes low when the conversion is complete, which is 3.6 m s max after the falling edge of convst , and new data from this conversion is available in the output latch of the AD7862. a read operation accesses this data. if the multiplexer select a0 is low, the first and second read pulses after the first conversion access the result from channel a (v a1 and v a2 v a1 v a2 v b1 v b2 t 3 t 1 t 2 t 4 t 5 t 6 t conv = 3.6? t 7 convst busy a0 cs rd data 300ns 400ns figure 5a. mode 1 timing operation diagram for high sampling performance
AD7862 C10C rev. 0 respectively). the third and fourth read pulses, after the second conversion and a0 high, access the result from channel b (v b1 and v b2 respectively). data is read from the part via a 12-bit parallel data bus with standard cs and rd signals. this data read operation consists of negative going pulse on the cs pin combined with a negative going pulse on the rd pin; this repeated twice will access the two 12-bit results. for the fastest throughput rate (with an internal clock of 3.7 mhz), the read operation will take 100 ns. the read operation must be com plete at least 300 ns before the falling edge of the next convst , and this gives a total time of 4 m s for the full throughput time (equivalent to 250 khz). this mode of operation should be used for high sampling applications. mode 2 operation (auto sleep after conversion) the timing diagram in figure 6 is for optimum performance in operating mode 2 where the part automatically goes into sleep mode once busy goes low after conversion and wakes-up before the next conversion takes place. this is achieved by keeping convst low at the end of the second conversion, whereas it was high at the end of the second conversion for mode 1 opera- tion. the operation shown in figure 6 shows how to a ccess data from both channels a and b followed by the auto sleep mode. one can also setup the timing to access data from channel a only or channel b only (see read options section on previous page) and then go into auto-sleep mode. the rising edge of convst wakes-up the part. this wake-up time is 2.5 m s when using an external reference and 5 ms when using the internal reference at which point the track/hold amplifiers go into their hold mode, provided the convst has gone low. the conversion takes 3.6 m s after this, giving a total of 6 m s (external reference, 5.0035 ms for internal reference) from the rising edge of convst to the conversion being complete, which is indicated by the busy going low. note that since the wake-up time from the rising edge of convst is 2.5 m s, if the convst pulse width is greater than 2.5 m s, the conversion will take more than the 6 m s (2.5 m s wake-up time + 3.6 m s conversion time) shown in the diagram from the rising edge of convst . this is because the track/hold amplifiers go into their hold mode on the falling edge of convst , and the conversion will not be complete for a further 3.6 m s. in this case the busy will be the best indicator for when the conversion is complete. even though the part is in sleep mode, data can still be read from the part. the read operation is identical to mode 1 operation and must also be complete at least 300 ns before the falling edge of the next convst to allow the track/hold amplifiers to have enough time to settle. this mode is very useful when the part is convert- ing at a slow rate, as the power consumption will be significantly reduced from that of mode 1 operation. dynamic specifications the AD7862 is specified and 100% tested for dynamic perfor- mance specifications as well as traditional dc specifications such as integral and differential nonlinearity. these ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters and spectrum analysis. these applica- tions require information on the adcs effect on the spectral content of the input signal. hence, the parameters for which the AD7862 is specified include snr, harmonic distortion, inter- modulation distortion and peak harmonics. these terms are discussed in more detail in the following sections. signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (f s /2) excluding dc. snr is depen- dent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical signal to noise ratio for a sine wave input is given by snr = (6.02 n + 1.76) db (1) where n is the number of bits. thus for an ideal 12-bit converter, snr = 74 db. v a1 v a2 v b1 v b2 t 3 t conv = 3.6? convst busy a0 cs rd data 300ns 400ns t 3 2.5?*/5ms** wake-up time t conv = 3.5? * *when using an external reference, wake-up time = 2.5? **when using an internal reference, wake-up time = 5ms figure 6. mode 2 timing where automatic sleep function is initiated
AD7862 C11C rev. 0 figure 7 shows a histogram plot for 8192 conversions of a dc input using the AD7862 with 5 v supply. the analog input was set at the center of a code transition. it can be seen that all the codes appear in the one output bin indicating very good noise performance from the adc. 746 756 747 748 749 750 751 752 753 754 755 9000 8000 0 4000 3000 2000 1000 6000 5000 7000 figure 7. histogram of 8192 conversions of a dc input the same data is presented in figure 8 as in figure 7 except that in this case the output data read for the device occurs during conversion. this has the effect of injecting noise onto the die while bit decisions are being made and this increases the noise generated by the AD7862. the histogram plot for 8192 conversions of the same dc input now shows a larger spread of codes. this effect will vary depending on where the serial clock edges appear with respect to the bit trials of the conversion process. it is possible to achieve the same level of performance when reading during conversion as when reading after conver- sion depending on the relationship of the serial clock edges to the bit trial points. the output spectrum from the adc is evaluated by applying a sine wave signal of very low distortion to the v ax/bx input that is sampled at a 245.76 khz sampling rate. a fast fourier trans- form (fft) plot is generated from which the snr data can be obtained. figure 9 shows a typical 2048 point fft plot of the AD7862 with an input signal of 10 khz and a sampling fre- quency of 245.76 khz. the snr obtained from this graph is 72.95 db. it should be noted that the harmonics are taken into account when calculating the snr. 745 755 746 747 748 749 750 751 752 753 754 0 4000 3000 2000 1000 6000 5000 7000 figure 8. histogram of the 8192 conversions with read during conversion ? ?20 0 12.2k 10k 30k 50k 70k 90k ?0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?10 100k f sample = 245760 f in = 10khz snr = ?2.95db thd = ?9.99db figure 9. AD7862 fft plot effective number of bits the formula given in equation 1 relates the snr to the number of bits. rewriting the formula, as in equation 2, it is possible to get a measure of performance expressed in effective number of bits (n). n = snr - 1. 7 6 6.02 (2) the effective number of bits for a device can be calculated directly from its measured snr. figure 10 shows a typical plot of effective number of bits versus frequency for an AD7862bn with a sampling frequency of 245.76 khz. the effective number of bits typically falls between 11.6 and 10.6 corresponding to snr figures of 71.59 db and 65.57 db. 0 1000 200 400 600 800 10.2 11.4 11.2 11.0 10.8 11.8 11.6 12.0 10.6 10.4 frequency ?khz enob figure 10. effective numbers of bits vs. frequency total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the AD7862, thd is defined as thd db () = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 and v 5 are the rms amplitudes of the second through the sixth harmonic. the thd is also derived from the fft plot of the adc output spectrum.
AD7862 C12C rev. 0 intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3 . . ., etc. intermodulation terms are those for which neither m or n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb) while the third order terms include (2 fa + fb), (2 fa C fb), (fa + 2 fb) and (fa C 2 fb). using the ccif standard where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the inter- modulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. in this case the input consists of two, equal amplitude, low distortion sine waves. figure 11 shows a typical imd plot for the AD7862. ? ?20 0 12.3k 10k 30k 50k 70k 90k ?0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?10 100k input frequencies f1 = 50010 hz f2 = 49110 hz f sample = 245760 hz snr = ?0.62db thd = ?9.22db imd: 2nd order term ?8.44 db 3rd order term ?6.20 db figure 11. AD7862 imd plot peak harmonic or spurious noise harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spec- trum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, the peak will be a noise peak. ac linearity plot when a sine wave of specified frequency is applied to the v in input of the AD7862, and several million samples are taken, a histogram showing the frequency of occurrence of each of the 4096 adc codes can be generated. from this histogram data, it is possible to generate an ac integral linearity plot as shown in figure 12. this shows very good integral linearity performance from the AD7862 at an input frequency of 10 khz. the absence of large spikes in the plot shows good differential linearity. sim- plified versions of the formulas used are outlined below. inl ( i ) = vi () - vo () 4096 () vf s () - vo () ? ? - i where inl ( i ) is the integral linearity at code i. v ( f s ) and v ( o ) are the estimated full-scale and offset transitions, and v ( i ) is the estimated transition for the i th code. v ( i ), the estimated code transition point is derived as follows: v ( i ) =- a cos p cum i () n ? ? where a is the peak signal amplitude, n is the number of histogram samples and cum i () = vn () n = 0 i ? occurrences 0 ?.1 ?.2 ?.3 ?.4 ?.5 0.5 0.4 0.3 0.2 0.1 lsb f in = 10 khz f in = 245.760 khz t a = 25 c figure 12. AD7862 ac inl plot power considerations in the automatic power-down mode the part may be operated at a sample rate that is considerably less than 200 khz. in this case, the power consumption will be reduced and will depend on the sample rate. figure 13 shows a graph of the power consumption versus sampling rates from 100 hz to 90 khz in the automatic power-down mode. the conditions are 5 v supply 25 c, and the data was read after conversion. 0.1 90 10 20 30 40 0 25 20 15 10 35 30 40 5 frequency ?khz power ?mw 50 60 70 80 figure 13. power vs. sample rate in auto power-down mode
AD7862 C13C rev. 0 microprocessor interfacing the AD7862 high speed bus timing allows direct interfacing to dsp processors as well as modern 16-bit microprocessors. suitable microprocessor interfaces are shown in figures 14 through 18. AD7862Cadsp-2100 interface figure 14 shows an interface between the AD7862 and the adsp-2100. the convst signal can be supplied from the adsp-2100 or from an external source. the AD7862 busy line provides an interrupt to the adsp-2100 when conversion is completed on all four channels. the four conversion results can then be read from the AD7862 using four successive reads to the same memory address. the following instruction reads one of the four results (this instruction is repeated four times to read all four results in sequence): mr0 = dm ( adc ) where mr0 is the adsp-2100 mr0 register, and adc is the AD7862 address. optional dma0 dma13 dmd15 dmd0 dms en addr decode address bus adsp-2100 (adsp-2101/ adsp-2102) * additional pins omitted for clarity data bus convst cs db11 db0 rd busy AD7862* irqn dmrd (rd) a0 figure 14. AD7862Cadsp-2100 interface AD7862Cadsp-2101/adsp-2102 interface the interface outlined in figure 14 also forms the basis for an interface between the AD7862 and the adsp-2101/adsp-2102. the read line of the adsp-2101/adsp-2102 is labeled rd . in this interface, the rd pulse width of the processor can be programmed using the data memory wait state control register. the instruction used to read one of the four results is outlined for the adsp-2100. AD7862Ctms32010 interface an interface between the AD7862 and the tms32010 is shown in figure 15. once again, the convst signal can be supplied from the tms32010 or from an external source, and the tms32010 is interrupted when both conversions have been comp leted. the following instruction is used to read the conver- sion res ults from the AD7862: in d,adc where d is data memory address, and adc is the AD7862 address. optional pa0 pa2 d15 d0 men en addr decode address bus tms32010 * additional pins omitted for clarity data bus convst cs db11 db0 rd busy AD7862* int den a0 figure 15. AD7862Ctms32010 interface AD7862Ctms320c25 interface figure 16 shows an interface between the AD7862 and the tms320c25. as with the two previous interfaces, conversion can be initiated from the tms320c25 or from an external source, and the processor is interrupted when the conversion sequence is completed. the tms320c25 does not have a separate rd output to drive the AD7862 rd input directly. this has to be generated from the processor strb and r/ w outputs with the addition of some logic gates. the rd signal is or-gated with the msc signal to provide the one wait state required in the read cycle for correct interface timing. conver- sion results are read from the AD7862 using the following instruction: in d,adc where d is data memory address and adc is the AD7862 address. a0 a15 d15 d0 is en addr decode address bus optional data bus convst cs db11 db0 rd busy AD7862* tms320c25 *additional pins omitted for clarity intn r/w strb msc ready a0 figure 16. AD7862Ctms320c25 interface
AD7862 C14C rev. 0 some applications may require that the conversion be initiated by the microprocessor rather than an external timer. one option is to decode the AD7862 convst from the address bus so that a write operation starts a conversion. data is read at the end of the conversion sequence as before. figure 18 shows an example of initiating conversion using this method. note that for all interfaces, it is preferred that a read operation not be attempted during conversion. AD7862Cmc68000 interface an interface between the AD7862 and the mc68000 is shown in figure 17. as before, conversion can be supplied from the mc68000 or from an external source. the AD7862 busy line can be used to interrupt the processor or, alternatively, software delays can ensure that conversion has been completed before a read to the AD7862 is attempted. because of the nature of its interrupts, the 68000 requires additional logic (not shown in figure 18) to allow it to be interrupted correctly. for further information on 68000 interrupts, consult the 68000 users manual. the mc68000 as and r/ w outputs are used to generate a separate rd input signal for the AD7862. cs is used to drive the 68000 dtack input to allow the processor to execute a normal read operation to the AD7862. the conversion results are read using the following 68000 instruction: move.w adc,d0 where d0 is the 68000 d0 register, and adc is the AD7862 address. a0 a15 d15 d0 en addr decode address bus optional data bus convst cs db11 db0 rd AD7862* mc68000 *additional pins omitted for clarity dtack r/w as a0 figure 17. AD7862Cmc68000 interface AD7862C80c196 interface figure 18 shows an interface between the AD7862 and the 80c196 microprocessor. here, the microprocessor initiates conversion. this is achieved by gating the 80c196 wr signal with a decoded address output (different to the AD7862 cs address). the AD7862 busy line is used to interrupt the microprocessor when the conversion sequence is completed. d15 d0 addr decode address bus address/data bus convst cs db11 db0 rd AD7862* 80c196 *additional pins omitted for clarity wr rd a0 a15 a1 figure 18. AD7862C8086 interface vector motor control the current drawn by a motor can be split into two compo- nents: one produces torque, and the other produces magnetic flux. for optimal performance of the motor, these two compo- nents should be controlled independently. in conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables; however, both the torque and flux are functions of current (or voltage) and frequency. this coupling effect can reduce the performance of the motor because, if the torque is increased by increasing the frequency, for example, the flux tends to decrease. vector control of an ac motor involves controlling phase in addition to drive and current frequency. controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux components. the AD7862, with its four-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. a block diagram of a vector motor control application using the AD7862 is shown in figure 19. the position of the field is derived by determining the current in each phase of the motor. only two phase currents need to be measured because the third can be calculated if two phases are known. v a1 and v a2 of the AD7862 are used to digitize this information. simultaneous sampling is critical to maintain the relative phase information between the two channels. a current sensing isolation amplifier, transformer or hall effect sensor is used between the motor and the AD7862. rotor information is obtained by measuring the voltage from two of the inputs to the motor. v b1 and v b2 of the AD7862 are used to obtain this information. once again, the relative phase of the two channels is important. a dsp microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7862.
AD7862 C15C rev. 0 voltage attenuators dac dac dac torque setpoint a1 v v b2 v b1 v a2 *additional pins omitted for clarity torque & flux control loop calculations & two to three phase information transformation to torque & flux current components flux setpoint drive circuitry isolation amplifiers AD7862* dsp microprocessor i c i b i a v b v a 3 phase motor figure 19. vector motor control using the AD7862 multiple AD7862s figure 20 shows a system where a number of AD7862s can be configured to handle multiple input channels. this type of configuration is common in applications such as sonar, radar, etc. the AD7862 is specified with typical limits on aperture delay. this means that the user knows the difference in the sampling instant between all channels. this allows the user to maintain relative phase information between the different channels. a common read signal from the microprocessor drives the rd input of all AD7862s. each AD7862 is designated a unique address selected by the address decoder. the reference output of AD7862 number 1 is used to drive the reference input of all other AD7862s in the circuit shown in figure 20. one vref pin can drive several AD7862 ref in pins. alternatively, an external or system reference can be used to drive all vref inputs. a common reference ensures good full-scale tracking between all channels. AD7862(1) AD7862(2) AD7862(n) cs rd cs rd cs rd rd address vref ref in ref in address decode v a1 v b1 v a2 v b2 v a1 v b1 v a2 v b2 v a1 v b1 v a2 v b2 figure 20. multiple AD7862s in multichannel system
AD7862 C16C rev. 0 outline dimensions dimensions shown in inches and (mm). c2211C12C10/96 printed in u.s.a. 28-pin plastic dip (n-28) 28 1 14 15 1.565 (39.70) 1.380 (35.10) 0.580 (14.73) 0.485 (12.32) pin 1 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) min seating plane 0.250 (6.35) max 0.100 (2.54) bsc 0.070 (1.77) max 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 28-pin cerdip (q-28) 28 114 15 0.610 (15.49) 0.500 (12.70) pin 1 0.005 (0.13) min 0.100 (2.54) max 15 0 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225 (5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) 28-pin small outline package (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-pin shrink small outline package (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0

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